TFS Takasago Fluidic Systems

For Efficient Solenoid Valve Operation - Hit and Hold Circuits

August 10, 2023

Hit and Hold Circuits

One characteristic of solenoid valves is that once valves are energized to full power, they remain activated even if the voltage is dropped to a lower level called holding voltage. Hit and Hold circuits use this characteristic to automatically maintain valves status at their holding voltage.


  1. ① Reduced power consumption
  2. ② Decreased coil heat dissipation
  3. ③ Enhanced response time
  4. ④ Higher operating pressure

The built-in timer of Hit and Hold circuits automatically drops the rated voltage to the holding voltage, after a very short period of time. Hit and Hold circuits can be incorporated with lead wires or installed inside the actuator case. Please contact us for more details to meet your needs.


Timing Diagram

Hit and Hold Circuits - Timing Diagram

Note: Details such as specifications, etc., may be changed without notice.


When the power supply voltage (Vi) is supplied, the output voltage (Vo) is supplied to the circuit after the delay time (Td). After the startup time (T1) preset in the circuit, the voltage value is averaged by PWM (Pulse Width Modulation) control during the holding time (T2) until the power supply is stopped.


Specification

Input 5~27 VDC
Inrush Time 100 or 300 ms
Output 30%, 40%, 50% of Input Voltage

Note: Details such as specifications, etc., may be changed without notice.

Dimensions

Hit and Hold Circuits - Timing Dimensions

Note: Details such as specifications, etc., may be changed without notice.