- Technical Information
- For Efficient Solenoid Valve Operation - Hit and Hold Circuits
For Efficient Solenoid Valve Operation - Hit and Hold Circuits
One characteristic of solenoid valves is that once valves are energized to full power, they remain activated even if the voltage is dropped to a lower level called holding voltage. Hit and Hold circuits use this characteristic to automatically maintain valves status at their holding voltage.
- ① Reduced power consumption
- ② Decreased coil heat dissipation
- ③ Enhanced response time
- ④ Higher operating pressure
The built-in timer of Hit and Hold circuits automatically drops the rated voltage to the holding voltage, after a very short period of time. Hit and Hold circuits can be incorporated with lead wires or installed inside the actuator case. Please contact us for more details to meet your needs.
Timing Diagram
Note: Details such as specifications, etc., may be changed without notice.
When the power supply voltage (Vi) is supplied, the output voltage (Vo) is supplied to the circuit after the delay time (Td). After the startup time (T1) preset in the circuit, the voltage value is averaged by PWM (Pulse Width Modulation) control during the holding time (T2) until the power supply is stopped.
Specification
Input | 5~27 VDC |
Inrush Time | 100 or 300 ms |
Output | 30%, 40%, 50% of Input Voltage |
Note: Details such as specifications, etc., may be changed without notice.
Dimensions
Note: Details such as specifications, etc., may be changed without notice.